Future Trends in Computing - Summer 16

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Summer 16
Prof. Dr. Michael Gerndt, Dr. Josef Weidendorfer, Emily Mo-Hellenbrand, M.Sc., Alexander Pöppl, M.Sc., Isaías Alberto Comprés Ureña
Time and Place
Initial Meeting: January 26th, 09:00-10:00, room 02.07.023
Kick-Off Meeting: April 19th, 14:00-16:00, room 02.07.023
Presentations: see Schedule section below.
Students from Master Informatics (IN2107), Computational Science and Engineering (IN2183), and Bachelor Informatics (IN0014)
Semesterwochenstunden / ECTS Credits
2 SWS (2S) / 4 Credits


  • Max. number of participants: 12


In the last ten years the period of vast increases in processing power mostly achieved by increasing the clock frequency of a processor has come to an end. Instead, computer architectures are getting more complex in order to accommodate the growing demand for processing power. Modern CPUs typically have a wide range of SIMD instructions for fine-grained data parallelism, and are capable of executing several threads on each of their several cores. Memory accesses are passed through multiple cache levels to hide memory access latencies. In addition to that, hardware specialized in performing massively parallel computations is getting more and more popular. Examples are GPUs and accelerators such as the Xeon Phi. In the HPC context, several nodes, each with its own CPU(s) and GPU(s) may be joined into a cluster.

Regular programming techniques and paradigms are no longer sufficient to fully utilize this hardware. Frameworks such as OpenCL take the structure and heterogeneity of the underlying hardware into account and provide the programming environment to expose all available resources, such as GPUs and accelerators. Novel approaches (such as invasive computing) expose the allocation of resources to the users, allowing them to request required resources and, by offering the reallocation of resources at runtime, enabling them to adapt to changing computing demands.

The behavior of the hardware at runtime also needs to be considered. Modern Cluster architectures are not necessarily capable to run at peak utilization 100% of the time. To avoid the overheating of the hardware and the resulting degradation of the silicon, the clock frequency of the CPU may be drastically reduced, or single nodes may even be shut down completely for a time. Taking these problems into account is an additional challenge developers face today.

Background: The seminar will (partly) discuss research executed in the collaborative research unit Invasive Computing funded by the German Research Foundation (DFG).


  • Fault Tolerance
  • Resource Aware Computing Concepts
  • Dark Silicon
  • Energy Aware Computing Techniques in HPC
  • Task-Based Runtime Systems
  • PGAS
  • Heterogeneous Computing
  • Actor-based Programming model
  • MIC architectures (Intel Xeon Phi)
  • MPI at Exascale
  • DSLs for HPC (ExaStencils)
  • Modeling vs. Automatic Tuning in HPC


Consider the Invasive Computing homepage. We encourage independent research and review of the available literature.


Time Place Description Material
19.04.2016, 14:00 - 16:00 MI 02.07.023 Kick-Off Meeting -
30.04.2016, 18:00 N\A Submission of paper title and outline -
15.06.2016, 18:00 N\A Submission of paper release candidate -
30.06.2016, 18:00 N\A Submission of paper final version -
21.06.2016, 14:00 - 16:00 MI 02.07.023 Presentation (1) -- (2) -- -
24.06.2016, 14:00 - 16:00 MI 01.13.010 Presentation (1) -- (2) -- -
28.06.2016, 14:00 - 16:00 MI 02.07.023 Presentation (1) -- (2) -- -
01.07.2016, 14:00 - 16:00 MI 01.13.010 Presentation (1) -- (2) -- -
05.07.2016, 14:00 - 16:00 MI 02.07.023 Presentation (1) -- (2) -- -
08.07.2016, 14:00 - 16:00 MI 01.13.010 Presentation (1) -- (2) -- -
  • Note 1: Please send all submission to your supervisor and CC Alexander Pöppl, M.Sc..
  • Note 2: Presentation slides are not subject to formal submission, but they will be graded as part of your presentation. You're strongly advised to consult your supervisor for the content of your slides.

Important Deadlines

Detailed deadlines will be posted later. These preliminary deadlines are subject to change.

  • End of April: submission of paper topic and outline.
  • Beginning of June: submission of paper (release candidate) for review.
  • End of June: submission of final paper.

Note: Failure to meet these deadlines may result in grade deduction or failure of the course.


  • Course language: English
  • Independent literature research
  • Paper: Total 6-10 pages (max 10 pages). IEEE format double-column (see link below) required.
  • Presentation: 30 minutes talk + 15 minutes discussion
  • Mandatory attendance: Participants must attend all presentations. Absence may be approved for "good" reasons with a prior discussion to the supervisors. For absence due to sickness, a doctor's attest must be provided. Unapproved absence will result in grade deduction or failure.