Future Trends in HPC - Summer 18
- Summer 18
- Alexander Pöppl, M.Sc., Emily Mo-Hellenbrand, M.Sc., TBA
- Time and Place
- Initial Meeting: Wednesday, January 31st 2018, 10:00-11:00, MI 01.09.014
- Kick-Off Meeting: Monday, April 9th 2018, 10:00-12:00, MI 02.07.023
- Presentations: see Schedule section below.
- Students from Master Informatics (IN2107), Computational Science and Engineering (IN2183), and Bachelor Informatics (IN0014)
- Semesterwochenstunden / ECTS Credits
- 2 SWS (2S) / 4 Credits
- Max. number of participants: 12
In the last ten years the period of vast increases in processing power mostly achieved by increasing the clock frequency of a processor has come to an end. Instead, computer architectures are getting more complex in order to accommodate the growing demand for processing power. Modern CPUs typically have a wide range of SIMD instructions for fine-grained data parallelism, and are capable of executing several threads on each of their several cores. Memory accesses are passed through multiple cache levels to hide memory access latencies. In addition to that, hardware specialized in performing massively parallel computations is getting more and more popular. Examples are GPUs such as the NVidia Volta. In the HPC context, several nodes, each with its own CPU(s) and GPU(s) may be joined into a cluster.
Regular programming techniques and paradigms are no longer sufficient to fully utilize this hardware. Frameworks such as OpenCL take the structure and heterogeneity of the underlying hardware into account and provide the programming environment to expose all available resources, such as GPUs and accelerators. Novel approaches (such as invasive computing) expose the allocation of resources to the users, allowing them to request required resources and, by offering the reallocation of resources at runtime, enabling them to adapt to changing computing demands.
The behavior of the hardware at runtime also needs to be considered. Modern Cluster architectures are not necessarily capable to run at peak utilization 100% of the time. To avoid the overheating of the hardware and the resulting degradation of the silicon, the clock frequency of the CPU may be drastically reduced, or single nodes may even be shut down completely for a time. Taking these problems into account is an additional challenge developers face today.
Background: The seminar will (partly) discuss research executed in the collaborative research unit Invasive Computing funded by the German Research Foundation (DFG).
- MIC architectures (Intel Xeon Phi)
- Heterogeneous Computing
- Dark Silicon
- Energy Aware Computing Techniques in HPC
- Fault Tolerance
- Resource Aware Computing Concepts
- Beyond MPI: New Runtime Systems for HPC
- Mixed-Precision hardware acceleration for HPC
- DSLs for HPC
- MPI at Exascale
- Modeling vs. Automatic Tuning in HPC
- Exotic Hardware Architectures (e.g. Sunway TaihuLight)
- FPGAs in HPC
We encourage independent research and review of the available literature.
|Wed 31.01.2018||MI 01.09.014||Initial Meeting||-|
|Mon 09.04.2018||MI 02.07.023||Kick-Off Meeting||-|
|Sun 06.05.2018, 23:59||N\A||Submission of paper title and outline (no abstract)||-|
|Sun 17.06.2018, 23:59||N\A||Submission of paper final version (hard deadline)||-|
|Tue 19.06.2018, 10:00-12:00||MI 02.07.023||Presentations||-|
|Fri 22.06.2018, 12:00-14:00||MI 02.07.023||Presentations||-|
|Tue 26.06.2018, 10:00-12:00||MI 02.07.023||Presentations||-|
|Fri 29.06.2018, 12:00-14:00||MI 02.07.023||Presentations||-|
|Tue 03.07.2018, 10:00-12:00||MI 02.07.023||Presentations||-|
|Fri 06.07.2018, 12:00-14:00||MI 02.07.023||Presentations||-|
- Note 1: Please send all submission to your supervisor and CC Alexander Pöppl, M.Sc..
- Note 2: Presentation slides are not subject to formal submission, but they will be graded as part of your presentation. You're strongly advised to consult your supervisor for the content of your slides.
- Note 3: Missing submission deadlines may result in grade deduction or failure.
- Course language: English
- Independent literature research
- Paper: Total 6-10 pages (max 10 pages). IEEE format double-column (see link below) required.
- Presentation: 30 minutes talk + 15 minutes discussion
- Mandatory attendance: Participants must attend all presentations. Absence may be approved for "good" reasons with a prior discussion to the supervisors. For absence due to sickness, a doctor's attest must be provided. Unapproved absence will result in grade deduction or failure.
- Grading components (failing either component will result in failing the seminar):
- Paper final version - 60%
- Presentation (slides + talk) - 40%
- Grade deduction or Failure factors: bad attendance, missing deadlines, plagiarism
- Bonus factors: commitment (interaction with supervisor, participation in discussions, etc.), self-implemented code/examples, etc.