Next Generation High Performance Computing - Winter 17

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Winter 2017/18
Emily Mo-Hellenbrand, M.Sc., Alexander Pöppl, M.Sc., Isaías Alberto Comprés Ureña, Philipp Samfass, M.Sc., Dr. rer. nat. Arash Bakhtiari, Carsten Uphoff, M.Sc., Michael Obersteiner, M.Sc.
Time and Place
Schedule and locations are available in Moodle
Computational Science and Engineering (Seminar, module IN2183),
Informatics (Master-Seminar, module IN2107),
Max 12 participants.
Semesterwochenstunden / ECTS Credits
2 SWS (2S) / 5 ECTS (TUM participants)
TUM Online

News & Dates

  • IEEE format latex template is downloadable below.
  • Kick-off Meeting: Tuesday, October 17 at 13:00 PM in room MI 02.07.023
  • pre-course meeting: Friday, July 7th, 10:00-11:00 in MI 02.07.014


The first generation of exascale supercomputers is expected for the first half of the 2020s. These machines will impose major challenges on simulation codes in order to run efficiently. Many challenges arise from the operation at the physical limits of the hardware and severe energy efficiency constraints. In this seminar, we will focus on the main challenges of exascale computing and discuss the approaches and building block for tackling these challenges.

Background: The seminar will (partly) discuss research executed in the collaborative research unit Invasive Computing funded by the German Research Foundation (DFG), the German priority programme SPPEXA funded by the German Research Foundation (DFG) and the ExaHyPE Project funded by the European Union’s Horizon 2020 research and innovation programme.


Supervisor Topic Assigned To Paper Presentation
Alexander Pöppl, M.Sc. DSLs in HPC Philipp Trucksäß
Alexander Pöppl, M.Sc. Energy-Aware Computing in HPC Benedikt Kucis
Emily Mo-Hellenbrand, M.Sc. MIC architecture (Xeon Phi) Philipp Matthäus
Emily Mo-Hellenbrand, M.Sc. Resource-Aware Computing Concepts Elis Bengisu
Isaías Alberto Comprés Ureña MPI at Exascale Agnieszka Gaczol
Isaías Alberto Comprés Ureña Modelling vs. Autotuning in HPC Charlie Kolb
Philipp Samfass, M.Sc. Heterogeneous Computing Pekka Väänänen
Philipp Samfass, M.Sc. Beyond MPI: New Runtime Systems for HPC Canberk Demirsoy
Dr. rer. nat. Arash Bakhtiari Exotic Hardware Architectures for HPC Lucas Wolf CANCELED CANCELED
Dr. rer. nat. Arash Bakhtiari Dark Silicon Johannes Meßmer
Carsten Uphoff, M.Sc. FPGAs for HPC Shreyas Shenoy
Michael Obersteiner, M.Sc. Fault Tolerance Bernhard Jaeger


  • Language: English
  • Independent literature research
  • Paper: IEEE format (double-column) 5-10 pages. Max 10 pages including references.
  • Presentation: 30 minutes talk (hard limit) + 10 min discussion.
  • Mandatory attendance of all presentation sessions:
    • Must attend all 4 presentation sessions.
    • For absence due to sickness, a doctor's attest is required.
    • Inform/discuss with your supervisor and the course organizers (Alex, Emily) prior if you plan to skip a session with a good reason.
    • Absence without approval will result in grade penalty or failure of the course. Treat the present sessions as if you would treat an exam.

Time Plan

  • Nov 05, 2017 before 23:59 MEZ: submission of paper title and outline
  • Jan 14, 2018: submission of paper for review (not mandatory)
  • Jan 28, 2018 before 23:59 MEZ: submission of final paper (mandatory, hard deadline!)
    • Late submission will not be tolerated. Failure to meet the submission deadline will result in failure of the course.
  • Presentation sessions:
    • Session 1: Jan 30, 2018, Tuesday, 13:00-15:00, MI 02.07.023
    • Session 2: Feb 02, 2018, Friday, 10:00-12:00, MI 02.07.023
    • Session 3: Feb 06, 2018, Tuesday, 13:00-15:00, MI 02.07.023
    • Session 4: Feb 09, 2018, Friday, 10:00-12:00, MI 02.07.023
    • 3 talks per session. Each talk 40 min (30 min talk + 10 min discussion).


  • Major components: final paper submission, presentation (slides + talk)
    • Submission of presentation slides is not required. However, your slides will be graded as part of your presentation.
  • Failure: miss paper submission deadline, bad attendance, plagiarism
  • Bonus: Self-implemented code/examples.