Resource-Aware Computing - Summer 15

Term

Summer 15

Lecturer

Univ.-Prof. Dr. Michael Bader, Dr. Josef Weidendorfer, Emily Mo-Hellenbrand, M.Sc., Alexander Pöppl, M.Sc.

Time and Place

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Initial Meeting: January 21st, 16:00, Room: t.b.a.

Kickoff: t.b.a.

Presentations: See Schedule section

Audience

Students from Master Computational Science and Engineering (IN2183), Informatics (IN2107), and Bachelor Informatics (IN0014)

Tutorials

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Exam

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Semesterwochenstunden / ECTS Credits

2 SWS (2S) / 4 Credits

TUMonline

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News

• Max. number of participants: 12

Description

In the last ten years the period of vast increases in processing power mostly achieved by increasing the clock frequency of a processor has come to an end. Instead, computer architectures are getting more complex in order to accommodate the growing demand for processing power. Modern CPUs typically have a wide range of SIMD instructions for fine-grained data parallelism, and are capable of executing several threads on each of their several cores. Memory accesses are passed through multiple cache levels to hide memory access latencies. In addition to that, hardware specialized in performing massively parallel computations is getting more and more popular. Examples are GPUs and accelerators such as the Xeon Phi. In the HPC context, several nodes, each with its own CPU(s) and GPU(s) may be joined into a cluster.

Regular programming techniques and paradigms are no longer sufficient to fully utilize this hardware. Frameworks such as OpenCL take the structure and heterogeneity of the underlying hardware into account and provide the programming environment to expose all available resources, such as GPUs and accelerators. Novel approaches (such as invasive computing) expose the allocation of resources to the users, allowing them to request required resources and, by offering the reallocation of resources at runtime, enabling them to adapt to changing computing demands.

The behavior of the hardware at runtime also needs to be considered. Modern Cluster architectures are not necessarily capable to run at peak utilization 100% of the time. To avoid the overheating of the hardware and the resulting degradation of the silicon, the clock frequency of the CPU may be drastically reduced, or single nodes may even be shut down completely for a time. Taking these problems into account is an additional challenge developers face today.

Background: The seminar will (partly) discuss research executed in the collaorative research unit Invasive Computing funded by the German Research Foundation (DFG).

Schedule

Date	Description	Material
21.01.2015	Initial Meeting	-
t.b.a.	Kick-Off Meeting	-

Topics

• Invasive Computing: Concepts

• Invasive Computing: The Framework

• Dark silicon (hardware, current Trends, etc)

• Faults and Fault-Tolerance

• Resource management for shared-/distributed-memory architectures

• Resource management for heterogeneous architectures

• Invasive algorithms

• Invasive Network-on-a-Chip architectures (iNoCs)

• Hardware-aware security mechanisms

• Heterogeneous computing frameworks: OpenCL

• Characterization of problems and extraction of patterns

• Power Saving by Dynamic Voltage and Frequency Scaling (DVFS) and Power Capping (PC)

Literature

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Requirements

For successful completion of the seminar course you have to fulfill the following tasks:

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The paper template is available here. Usage of Latex is required.