Future Trends in HPC - Summer 17

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Summer 17
Alexander Pöppl, M.Sc., Emily Mo-Hellenbrand, M.Sc., Dr. Josef Weidendorfer, Isaías Alberto Comprés Ureña, Philipp Samfass, M.Sc., Chaulio Ferreira, M.Sc., Nikola Tchipev, M.Sc., Carsten Uphoff, M.Sc., Michael Obersteiner, M.Sc.
Time and Place
Initial Meeting: Tue, Jan 24th, 10:00-11:00, MI 02.07.023
Initial Meeting (repeated, attend only if you miss the first one): Fri, Feb 3rd, 10:00-11:00, MI 02.07.023
Kick-Off Meeting: Wed, April 26th, 14:00-16:00, MI 02.07.023
Presentations: see Schedule section below.
Students from Master Informatics (IN2107), Computational Science and Engineering (IN2183), and Bachelor Informatics (IN0014)
Semesterwochenstunden / ECTS Credits
2 SWS (2S) / 4 Credits


  • Max. number of participants: 12


In the last ten years the period of vast increases in processing power mostly achieved by increasing the clock frequency of a processor has come to an end. Instead, computer architectures are getting more complex in order to accommodate the growing demand for processing power. Modern CPUs typically have a wide range of SIMD instructions for fine-grained data parallelism, and are capable of executing several threads on each of their several cores. Memory accesses are passed through multiple cache levels to hide memory access latencies. In addition to that, hardware specialized in performing massively parallel computations is getting more and more popular. Examples are GPUs and accelerators such as the Xeon Phi. In the HPC context, several nodes, each with its own CPU(s) and GPU(s) may be joined into a cluster.

Regular programming techniques and paradigms are no longer sufficient to fully utilize this hardware. Frameworks such as OpenCL take the structure and heterogeneity of the underlying hardware into account and provide the programming environment to expose all available resources, such as GPUs and accelerators. Novel approaches (such as invasive computing) expose the allocation of resources to the users, allowing them to request required resources and, by offering the reallocation of resources at runtime, enabling them to adapt to changing computing demands.

The behavior of the hardware at runtime also needs to be considered. Modern Cluster architectures are not necessarily capable to run at peak utilization 100% of the time. To avoid the overheating of the hardware and the resulting degradation of the silicon, the clock frequency of the CPU may be drastically reduced, or single nodes may even be shut down completely for a time. Taking these problems into account is an additional challenge developers face today.

Background: The seminar will (partly) discuss research executed in the collaborative research unit Invasive Computing funded by the German Research Foundation (DFG).


Supervisor Topic Assigned To Paper Slides
Alexander Pöppl, M.Sc. DSLs for HPC Christopher Polster
Alexander Pöppl, M.Sc. PGAS Moritz Schwab
Alexander Pöppl, M.Sc. Actor-Based Programming Model Ayman Noureldin
Emily Mo-Hellenbrand, M.Sc. Resource aware Computing Concepts Simeon Mahov
Emily Mo-Hellenbrand, M.Sc. Hardware Accelerated Machine Learning Dmytro Sashko
Dr. Josef Weidendorfer Energy Aware Computing Techniques Fukushi Sato
Dr. Josef Weidendorfer Dark Silicon Anahit Hayrapetyan
Isaías Alberto Comprés Ureña Modelling vs. Autotuning in HPC Calvin Devereux
Isaías Alberto Comprés Ureña MPI at Exascale Asad Ali
Philipp Samfass, M.Sc. Task-based runtime system Michal Waleszczuk
Philipp Samfass, M.Sc. Heterogeneous Computing Hasan Ashraf
Carsten Uphoff, M.Sc. FPGAs for HPC Josef Stark
Chaulio Ferreira, M.Sc. Exotic Hardware Ruidong Zhang
Michael Obersteiner, M.Sc. Fault Tolerance in HPC Peter Münch
Nikola Tchipev, M.Sc. MIC Architectures Raghavendra Kamath Bola


We encourage independent research and review of the available literature.


Time Place Description Material
26.04.2017, 14:00 - 16:00 MI 02.07.023 Kick-Off Meeting -
05.05.2017, 18:00 N\A Submission of paper title and outline (no abstract) -
18.06.2017, 18:00 N\A Submission of paper final version -
Tue 20.06.2017, 8:30-10:00 MI 00.08.055 Presentations: Polster, Noureldin -
Wed 21.06.2017, 14:30-16:00 MI 02.07.023 Presentations: Schwab, Mahov -
Tue 27.06.2017, 8:30-10:00 MI 00.08.055 Presentations: Sashko, Sato -
Wed 28.06.2017, 14:30-16:00 MI 02.07.023 Presentations: Hayrapetyan, Devereux -
Tue 04.07.2017, 8:30-10:00 MI 00.08.055 Presentations: Ali, Waleszczuk -
Wed 05.07.2017, 14:30-16:00 MI 02.07.023 Presentations: Ashraf, Stark, Zhang -
Tue 11.07.2017, 8:30-10:00 MI 00.08.055 Presentations: Münch, Kamath Bola -
Wed 12.07.2017, 14:30-16:00 MI 02.07.023 Presentation: ... -
  • Note 1: Please send all submission to your supervisor and CC Alexander Pöppl, M.Sc..
  • Note 2: Presentation slides are not subject to formal submission, but they will be graded as part of your presentation. You're strongly advised to consult your supervisor for the content of your slides.
  • Note 3: Missing submission deadlines may result in grade deduction or failure.


  • Course language: English
  • Independent literature research
  • Paper: Total 6-10 pages (max 10 pages). IEEE format double-column (see link below) required.
  • Presentation: 30 minutes talk + 15 minutes discussion
  • Mandatory attendance: Participants must attend all presentations. Absence may be approved for "good" reasons with a prior discussion to the supervisors. For absence due to sickness, a doctor's attest must be provided. Unapproved absence will result in grade deduction or failure.


  • Grading components (failing either component will result in failing the seminar):
    • Paper final version - 60%
    • Presentation (slides + talk) - 40%
  • Grade deduction or Failure factors: bad attendance, missing deadlines, plagiarism
  • Bonus factors: commitment (interaction with supervisor, participation in discussions, etc.), self-implemented code/examples, etc.