SC²S Colloquium - November 18, 2016

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Date: November 18, 2016
Room: 02.07.023
Time: 3:00 pm, s.t.

Arslan Ali Syed: Fast Quasi-Newton Method for Partitioned Analog Circuit Simulation in Time Domain

With the advancements of integrated circuit design, the need for fast analog simulation has become indispensable for the semiconductor industry. One of the techniques used for this purpose involves partitioning the circuit into block bordered diagonal (BBD) form, which allows for faster sequential and parallel simulations. For solving the BBD linear system built during each Newton iteration of the transient (time-dependent) analysis, mixed direct/iterative method is used. The fundamental question in this regard is whether a further speedup could be achieved by skipping some of the blocks during the computation. Therefore, a fast Quasi-Newton method for the transient analysis of partitioned circuits, based upon bypassing some of the blocks, is presented. A hybrid scheme is proposed which, for the current iteration, uses previously calculated function values from the last iteration with some of the bypassed blocks and a linearly extrapolated estimation with the others. For the bypassed blocks, the Jacobian matrix of the last iteration is used. The proposed method showed an average performance gain of around 18 percent for the total transient analysis time in the simulation.